1. Field of the Invention
The present invention is related to the field of computer systems. In particular, the present invention is related to a method and apparatus for writing data to memory.
2. Description of the Related Art
A processor, for example, a MIPS processor manufactured by MIPS Technologies, Inc., of 2011 N. Shoreline Blvd, Mountain View, Calif. 94039-7311, outputs eight data words during sequential clock cycles of a burst mode write cycle to memory. One skilled in the art will appreciate that a burst mode write cycle occurs when a processor outputs a burst of data, as compared with a word of data, for a limited amount of time. However, prior to storing the data words in memory, the memory, such as Synchronous Dynamic Random Access Memory (SDRAM), has to be precharged and activated. Precharging and activating SDRAM comprises a memory controller issuing precharge and activate commands to the SDRAM. These commands take at least four system clock cycles to prepare the SDRAM to begin accepting data.
FIG. 1 illustrates a bus architecture called a separate bus architecture, wherein the processor bus and the memory bus are separate and distinct from each other. In such a bus architecture, when the processor 105 accesses memory 115, for example, a SDRAM bank, and the SDRAM bank is unavailable to receive data output from the processor, the data is temporarily stored in a buffer (not shown) within memory controller 110. Concurrently with storing data in the memory controller's buffer, the memory controller issues a precharge and activate command to prepare the SDRAM bank to receive the data being stored. As soon as the SDRAM is available to receive data, i.e., after the precharge and activate commands have been issued to the SDRAM bank, and before the entire burst of data is stored in the buffer within the memory controller 110, data from the buffer in the memory controller is written to SDRAM. The separate bus architecture makes it possible to write data to the SDRAM bank as soon as the SDRAM bank is available to receive data, while the processor is concurrently outputting data to the buffer in the memory controller. Hence, this bus architecture takes fewer system clock cycles for a processor's burst write.
However, the separate bus architecture has the disadvantage of requiring additional system clock cycles when reading data, because the data from the SDRAM has to be first read into a buffer in the memory controller prior to being input into the processor.
To shorten the data read process, a bus architecture called the shared bus architecture, as illustrated in FIG. 2, is employed. The shared bus architecture improves the data read performance but has the disadvantage of requiring additional system clock cycles during burst mode write (hereafter burst write) cycles, as discussed below.
During a burst write in a shared bus architecture 200, when a burst of data is to be written to memory 215 from processor 205 and the memory bank is unavailable, for example, due to the memory bank not being precharged and activated, the burst of data is temporarily stored in a buffer (not shown) in a memory controller 210. The entire burst of data is stored in the buffer, even though sometime during the burst write, the memory may become available to receive the data. The reason for this is that during the burst write, processor 205 has control of the bus, and only relinquishes control of the bus to the memory controller when the entire burst of data has been stored in the buffer. What is needed, therefore, is a method and apparatus to speed up the burst mode write by a processor in the shared bus architecture.